1. Field of the Invention
The present invention relates generally to data processing systems and more particularly relates to data processing systems employing cache memory.
2. Description of the Prior Art
It has been shown that the use of a small high speed memory, often called a cache memory, between an instruction processor and the much slower main memory tends to enhance performance. Instructions and data present within the cache memory at the time of requested access by the instruction processor are furnished much more quickly than those instructions and data which must be obtained from main memory.
To obtain maximum benefit from the use of a cache memory, it is desirable to anticipate which memory locations will be accessed by the instruction processor so that they may be preloaded into the cache memory. U.S. Pat. No. 3,806,888 issued to Brickman et al, shows an early data processing system employing a cache memory between the main memory (i.e. backing store) and the instruction processor (i.e. central processing unit). In this system, real memory is segmented into blocks or pages. If the instruction processor requests access to one data element of a block, the entire block is automatically transferred to the cache memory for subsequent use by the instruction processor. U.S. Pat. No. 4,225,922 issued to Porter attempts to improve upon the basic cache approach by segmenting the cache memory and by buffering cache commands. U.S. Pat. No. 4,354,232 issued to Ryan also buffers cache control commands.
The prefetching of data may be further complicated by variable length elements. U.S. Pat. No. 4,189,772 issued to Liptay attempts to address this problem by buffering the input to the cache memory. A decoder element is added by U.S. Pat. No. 4,437,149 issued to Pomerene et al, between the main memory and the cache memory to partially decode instructions before complete loading of the cache memory.
The cache memory and cache controller are placed on the same substrate in U.S. Pat. No. 5,025,366 issued to Baror. U.S. Pat. No. 4,905,188 issued to Chuang et al, describes a chip design for optimization of the hardware construction.
A multiprocessor system is shown in U.S. Pat. No. 5,023,776 issued to Gregor. The individual instruction processors have dedicated (i.e. L1) cache memories. Shared (i.e. L2) cache memories are interposed between the dedicated cache memories and the main (i.e. L3) memory. Write buffers are employed in parallel with the L2 caches. Multiple sequential writes bypass the L2 cache and proceed directly to the L3 memory through the write buffers.
In each of the prior art approaches, however, prefetching of the correct data continues to be a problem, along with the delay associated with the transfer of the prefetched data into the cache memory. A further problem is the difficulty in holding the instruction processor for a period of time necessary to preload the entire block of data containing the requested data element.